During the manufacture of integrated circuit devices, notably RF or analog-mixed signal (AMS) integrated circuit devices, it is often desired to include capacitors in the circuits. Increasingly this is being achieved using MIM capacitors, especially high dielectric constant (high-k) MIM capacitors.
A number of different architectures have been proposed for integrating MIM capacitors during semiconductor manufacturing processes. In some of these architectures a MIM capacitor is formed by providing a lower plate, a dielectric layer and an upper plate stacked up within an interlayer dielectric layer located between two metal (interconnect) layers. For example, such a MIM capacitor may be provided in the interlayer dielectric between the penultimate metal layer, designated “LM-1”, and the last metal layer designated “LM” (counting from the wafer outwards).
In the present document, the case where an integrated MIM capacitor is formed between the LM and LM-1 layers will be used as an illustration. However, the MIM capacitor can be formed between any two of the metallization layers in the stack formed on the semiconductor wafer. Furthermore, in the present document the expression “metallization layer” will be used both to designate the metal conductors of a particular layer as well as the dielectric into which the metallization will be patterned/filled.
FIG.1 illustrates the above-mentioned architecture in which a MIM capacitor is provided in the interlayer dielectric (ILD) between the LM and LM-1metallization layers.
In the architecture illustrated in FIG.1, the LM-1 layer consists of a dielectric 10, typically formed of a low dielectric-constant (low-k) or ultra-low dielectric constant (ULK) material (or, possibly, of a material such as SiO2, or fluorosilicate glass (FSG, i.e. fluorine-doped SiO2)), in which conductive metal traces or pads 15 are provided, typically made of Al or Cu. A layer 18 of SiC, SiCN, SiN, or the like, is provided on the LM-1 layer so as to prevent oxidation of the conductive wiring/pads 15 or diffusion of material therefrom into overlying material. An interlayer dielectric layer ILD, typically made of SiO2, or, for example, fluorosilicate glass (FSG, i.e. fluorine-doped SiO2), is formed on the SiN layer 18 and consists of a first dielectric portion 20a, and a second dielectric portion 20b. On the dielectric layer 20a, there is a first metal layer 21 forming the bottom plate of a MIM capacitor, a capacitor dielectric layer 22, and a second metal layer 23 forming the top plate of the MIM capacitor. The top and bottom plates of the MIM capacitor are typically made of TiN and, nowadays, the capacitor dielectric is generally formed of a high-k material, such as Ta2O5, Al2O3, or HfO2.
An etch-stop barrier layer 24 is formed over the MIM capacitor and is generally made of the same kind of material as can be used for layer 18, e.g. SiC. The interlayer dielectric layer ILD may be topped by an etch-stop layer 28, typically made of SiC or the like, serving to stop the etching process when trenches are etched for the conductors of the LM metallization layer. The LM dielectric layer 30 is formed on the SiC layer 28. Conductive metallic traces and/or pads 35 are formed in the LM layer. Vias VTP, VBP, and VM, extend from certain of the conductive traces 35 of the LM layer to the top plate of the MIM capacitor, the bottom plate of the MIM capacitor and to conductive traces 15 of the LM-1 layer, respectively.
FIGS. 2A to 2I illustrate stages in a conventional method for fabricating the architecture of FIG.1. According to the conventional process, a semiconductor wafer (not shown) is processed in a conventional manner with a view to producing desired circuit elements for a number of integrated circuits. This involves doping of regions of the wafer and the formation of a number of metallization layers and interlayer dielectric layers over the wafer surface. FIG.2A illustrates the structure of a typical metallization layer LM-1 produced in this process, consisting of conductors 15 (typically made of Al or Cu) in a dielectric layer 10 (typically formed of SiO2, or a low-k material such as SiCOH), topped by a SiC barrier layer 18.
A portion of SiO2, interlayer dielectric 20a, is formed over the LM-1metallization layer by any convenient technique: for example, chemical vapour deposition (CVD). Then a stack of layers is formed on the dielectric layer 20a; the stack consists of a first metallic layer 21, a dielectric layer 22 and a second metallic layer 23, as illustrated in FIG.2B. Each of the first and second metallic layers may be a unitary layer or it may be a lamination of layers of different materials. Moreover, the material or materials used in the first and second metallic layers may be the same or different from each other.
Conventional photolithographic techniques are used to pattern the second metallic layer 23 into the top plate TP for the desired MIM capacitor, see FIG.2C. Next, as illustrated in FIG.2D, the wafer is coated with an etch-stop layer 24, generally made of the same kind of material as the layer 18 (e.g. SiC or the like), by any convenient process, e.g. CVD. Next, the etch-stop layer 24, first metallic layer 21 and the dielectric layer 22 are patterned, in a common set of processes, so as to define the bottom plate BP of the MIM capacitor and the capacitor dielectric CD. Then a second portion of interlayer dielectric 20b,, a further etch-stop layer 28 (e.g. made of SiC) and a further layer 30 of dielectric are deposited—see FIG.2F.
The metallization layer LM is formed in the top section of the structure shown in FIG.2F. In general it is desirable for the metallization layer LM overlying the MIM capacitor to include metallic contacts that are connected to the top plate of the MIM capacitor, to the bottom plate of the MIM capacitor, and to metallic traces in the LM-1 metallization layer. This can be achieved using conductive vias extending through the interlayer dielectric (formed by etching via holes in the interlayer dielectric and then filling them with a conductive material). Now, in order to minimize the number of process steps, it is generally desired to etch all the desired via holes through the interlayer dielectric layer ILD in a common etching process. Thus, in a single process it is necessary to etch at least one via hole EV1, extending to the top plate of the MIM capacitor, at least one via hole EV2, extending to the bottom plate of the MIM capacitor and at least one via hole EV3, extending to a metallic trace 15 in the next metallization layer down (LM-1 in this example), see FIG.2G.
Once the via holes have been etched, enlarged openings EP1, EP2, and EP3 are formed in the SiC layer 28 and dielectric layer 30 at the top ends of the via holes EV1, EV2, and EV3, and trenches EP1, EP2, and EP3, for any other desired conductive traces/pads in the LM metallization layer are formed, by photolithographic and etching processes (see FIG.2H). Then a metallic material (e.g. Al or Cu) is applied over the structure of FIG.2H, filing the via holes and trenches EP1, EP2, and EP3, as shown in FIG.2I. Finally, the wafer surface is polished, resulting in the overall architecture shown in FIG.1.
As mentioned above, during the conventional process for fabricating the MIM architecture of FIG.1, a single via-etching process is required to etch vias extending from the LM layer down to three different levels, namely to the MIM capacitor top plate, to the MIM capacitor bottom plate and to the metallization of the LM-1 layer. Moreover, the etching process is required to stop on two or more different materials, namely the metal forming the plates of the MIM capacitor and the metal of the metallization layer LM-1 (which, in general, will be a different material from the metal(s) used in the MIM capacitor top and bottom plates). The need to satisfy all of these requirements in a common etching process places considerable constraints on that process, notably in terms of finding an etching species that will have a suitable pattern of selectivities.